Fast Adder Architectures: Modeling and Experimental Evaluation

Nuno Roma and Tiago Dias and Leonel Sousa Dept. of Electrical and Computer Engineering, I.S.T. / INESC-ID R. Alves Redol, 9, 1000-029 Lisboa, Portugal Email: [email protected], [email protected], [email protected] Abstract— This paper presents a detailed comparison analysis of several fast adder architectures for high performance VLSI design. The evaluation of those architectures is firstly carried out based on a simple gate-count model for area and gatedelay units for time. The results obtained with such model were then validated by using two entirely different real-world implementation technologies, namely CMOS integrated circuits and Field Programmable Gate Arrays (FPGA). Experimental results show that among the modeled and evaluated topologies, the adder architecture based on the radix-2 redundant format converter offered the lowest delay when implemented with any of the considered technologies. However, it was also the topology that required the highest amount of hardware. The presented results can be seen as an invaluable resource in the selection of the most appropriate adder topology that will be used to implement a given arithmetic operation in a specified technology.